This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-093934, filed Mar. 30, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor integrated circuit, and more specifically, to a semiconductor integrated circuit operated under a plurality of power supply sources and comprising a complementary MIS logic circuit operated at low power supply voltage.
Recently, the number of semiconductor elements formed on a chip has significantly increased. Several hundreds of millions of semiconductor elements are integrated per chip in a gigabit-order semiconductor memory, and several tens of thousands to tens of millions of semiconductor elements are integrated per chip in a 64-bit microprocessor. The number of semiconductor elements formed on a chip can be improved by reducing the size of semiconductor elements. An MOS transistor having a gate length of 0.15 micrometers is now used in a 1 G-bit DRAM (Dynamic Random Access Memory). An MOS transistor having a gate length of 0.1 micrometer or less will be employed in the future as the number of semiconductor elements formed on a chip is further increased.
However, the miniaturized MOS transistors are degraded due to hot carriers and a dielectric film breakdown due to TDDB (time dependent dielectric breakdown). In addition, as a channel length of an FET decreases, a threshold voltage of the FET also decreases. To prevent the threshold voltage from decreasing, an impurity concentration of a substrate region or a channel region of the FET is increased. However, as the impurity concentration increases, a source/drain junction voltage of the FET also decreases.
Reducing a power supply voltage is effective in maintaining the reliability of miniaturized MOS transistors and FETS. More specifically, by reducing the power supply voltage, the electric field in a lateral direction between the source and drain is weakened preventing the generation of hot carriers. Furthermore, by reducing the power supply voltage, the electric field in a longitudinal direction between the gate and bulk is weakened preventing TDDB. Furthermore, a reverse bias voltage applied to the junction between the drain and bulk is decreased by reducing the power supply voltage. In this way, it is possible to cope with a decrease in a breakdown voltage of the junction.
Recently, the market for portable information devices has remarkably increased. Most of the portable information devices employ a lightweight power supply, such as a lithium ion battery having a high energy density. However, the three volts (3V) of the lithium ion battery is higher than the breakdown voltage of a miniaturized MOS transistor. Therefore, when the lithium ion battery is applied to a circuit comprising a miniaturized transistor, a power supply voltage converter must be used to reduce the voltage. The power consumed during the operation of a CMOS circuit used in a logic circuit is not only proportional to an operational frequency, but also proportional to the square of the power supply voltage. Therefore, reducing the power supply voltage significantly lowers the power consumption in the chip.
Using a portable device for a long time requires using a battery with a high energy density, having a highly efficient power supply voltage converter, and operating an integrated circuit at a low voltage. Power consumption can be saved further if a reduced power supply voltage can be used in a power-consuming microprocessor and base band LSI.
The portable information device also requires a memory device such as a DRAM or an SRAM in addition to logic circuits. However, unlike with logic circuits, attempts to reduce power consumption in memory devices have not been aggressively made. To reduce soft errors in a DRAM, a sufficient amount of electric charge must be kept in a cell in the DRAM. Furthermore, low speed operation at a low power supply voltage in the SRAM must be avoided.
Therefore, at present, only elements capable of operation at a power supply voltage of about 1.5V are put to practical use. However, since a logic circuit can operate at a voltage far smaller than the power supply voltage for a memory device, a multi-power source capable of supplying various power supply voltages is used in an LSI comprising memory circuits and logic circuits.
FIG. 1 shows a semiconductor integrated circuit 604, for use in portable information devices, in which an on-chip memory circuit 603 and a logic circuit 602 are integrated in the same chip. Its power supply system is also shown in FIG. 1.
The power supply system includes a lithium ion secondary battery 600 and a power supply voltage converter 601. The output voltage, 3V, of the lithium battery 600 is converted to 0.5V by the power supply voltage converter 601. The converted voltage is supplied to the logic circuit 602. Since the on-chip memory circuit 603 generally requires a power supply voltage of 1.5V to 2.0V or more for operation, a power supply voltage of 3V is supplied to the memory circuit 603 from the lithium battery 600.
In the circuit arrangement of FIG. 1, if the power supply voltage to the logic circuit can be reduced from 3V to about 0.5V, the power consumption during the operation time can be drastically reduced by 95%, in theory. However, if the power supply voltage for a general CMOS circuit operating at 3V to 2V is just simply reduced, the operation speed of the CMOS circuit is lowered or the operation stops.
To overcome these problems, a threshold voltage of a MOS transistor must be reduced along with a decrease in a power supply voltage. To construct a logic circuit that operates at a low power supply voltage of 0.5V, for example, a MOSFET having a threshold voltage of about 0.1 to 0.15V, which is about ⅓ of the threshold voltage of a conventional MOSFET, should be used.
However, with such a low threshold voltage, the leakage current during an off-time of a MOSFET drastically increases by a factor of 100 if an S factor, which determines a sub-threshold characteristic of a MOSFET, is 100 mA/decade, for example. Therefore, although the power consumption during an operation time is reduced simply by reducing the power supply voltage, the power consumption during a stand-by time is significantly increased. This means that the usable time of a device is shortened due to the stand-by time power consumption. Therefore, the reduced power supply voltage application as mentioned above is not suitable for semiconductor integrated circuits used in portable information devices.
FIG. 2 shows an improved circuit to overcome the aforementioned problems. In the circuit, an extremely low voltage of 0.5V is supplied to a semiconductor integrated circuit 705 by a power supply voltage converter 701 and a power supply voltage VD1 (0.5V) is supplied to a logic circuit 702. This attains low power consumption during an operation time.
Furthermore, a positive voltage generator 703 and a negative power voltage generator 704 are provided to generate a voltage that is greater than a power supply voltage VD1 and a voltage that is less than a ground potential VSS, respectively.
The supply voltages generated by the voltage generators 703 and 704 are applied to an n-well and a p-well of the logic circuit 702, respectively, to reduce an absolute value of a threshold voltage of the MOSFETs in the logic circuit 702 during a normal operation time to increase the operation speed. In addition, the absolute value of the threshold voltage of the MOSFETs within the logic circuit 702 is increased during the stand-by time to reduce the leakage current during the OFF-time to lower the power consumption.
However, when supplying an extremely low power supply voltage of 0.5V, problems usually occur. For example, a charge pump system is usually used for the positive voltage generator 703 and the negative voltage generator 704 in the semiconductor integrated circuit. However, the charge pump system does not have a sufficient driving capacity to control a well potential when the power supply voltage is as low as 0.5V. To increase the driving capacity of the charge pump system when the power supply voltage is as low as 0.5V, the size of the driver MOSFET must be increased to an extremely large size. Consequently, the layout areas of the voltage generators 703 and 704 become larger than that of the conventional circuit.
Furthermore, since a power supply voltage of 1.5V or more is required for the on-chip memory circuit, another power supply voltage is needed. In addition, since a power supply voltage for the logic circuit 702 is as low as 0.5V, the noise margin of the gate circuit may be reduced. In the worst case, depending upon the threshold voltage of the MOSFET within the logic circuit, the circuit cannot operate.
FIG. 3 shows a circuit diagram also designed to overcome the leakage current problem during the OFF-time. Three types of power supply voltages are provided in a semiconductor integrated circuit 805. A 3V power supply voltage (VDD) from a secondary battery 800 and a ground potential (VSS) are supplied to a memory circuit 804, which is integrated within the semiconductor integrated circuit 805. At the same time, a power supply voltage VD1 (0.5V) supplied from a power supply voltage converter 801 is connected to a power supply line VDDV for a logic circuit 802 via a p-channel MOSFET 803 having a high threshold voltage.
In the circuit of FIG. 3, before a stand-by time, it is necessary to save data of a flip-flop within the logic circuit 802 in the memory circuit 804 since the power supply to the logic circuit 802 is turned off during the stand-by time. After the data within the logic circuit 802 is saved in the memory circuit 804, the power supply voltage VDD is applied to the gate of the p-channel MOSFET 803, during the stand-by time, which turns off the MOSFET 803. At that time, the leakage current becomes extremely small since the leakage current is determined by the OFF-characteristics of the p-channel MOSFET 803 having a large threshold voltage.
Furthermore, the noise margin of the gate circuit may be insufficient since a power supply voltage for the logic circuit 802 is 0.5V. As a result, depending upon variation of the threshold voltage of the MOSFETs in the logic circuit 803, the circuit may not operate. Furthermore, when an extremely low voltage of 0.5V is supplied, the power supply voltage becomes noticeably reduced because of an on-resistance of the switch transistor 803. As a result, the circuit margin may further decrease or the power supply efficiency may decrease.
The reason the circuit margin of the logic gate decreases when the power supply voltage decreases to 0.5V will be explained more specifically. FIG. 4 is a graph showing a circuit noise margin obtained by a circuit simulation using a threshold voltage VthP of a p-channel MOSFET and a threshold voltage VthN of an n-channel MOSFET as parameters under the following conditions: a circuit having 4-input NAND gates and 4-input NOR gates formed using a 0.25 xcexcm process technique is operated under the worst conditions described later. The n-well potential is 0.45V and the p-well potential is 0.0V. The input signals other than the target signal are set so as to render the gate OFF. More specifically, the power supply voltage is applied to the NAND gate as an input signal and the ground potential is applied to the NOR gate as an input signal. The temperature of the MOSFET is set at 85xc2x0 C., which is an upper limit of a junction temperature, and the power supply voltage is 0.45V. It is assumed that the power supply voltage does not drop and the ground potential does not increase.
The noise margin is determined under the worst conditions where a noise source signal xe2x80x9cvnxe2x80x9d is applied as the input signal of the NAND gate and a noise source signal xe2x80x9cxe2x88x92vnxe2x80x9d is applied as the input signal of the NOR gate. From FIG. 4, it is found that the largest circuit noise margin is obtained when VthP=xe2x88x92VthN. More specifically, since the noise margin is about 0.135V at a threshold condition (i.e., VthP=xe2x88x920.10V, VthN=0.10V), which is suitable when the power supply voltage is 0.5V, the operation of the LSI can be ensured to some extent.
However, when the threshold voltage VthN of the n-channel MOSFET is shifted toward a minus side by about 0.3V, that is, VthP=xe2x88x920.10V, VthN=xe2x88x920.20V, the circuit margin is 20 mV, which is almost the same as the thermal noise. Furthermore, when the threshold voltage VthN is shifted by about 0.2V, that is, VthP=xe2x88x920.10V, VthN=xe2x88x920.10V, the circuit noise margin is 54 mV. As a matter of fact, not only does the temperature condition and power supply voltage change, but also, the power supply voltage decreases and the ground potential increases. In the worst-case condition, the noise margin decreases by about 50 mV. Therefore, even if the threshold voltage changes only by about 0.2V, it seems difficult to perform a normal operation of the circuit within the LSI.
As described above, even in a complementary MOS circuit having a sufficient circuit margin, the circuit margin sometimes becomes almost zero at a power supply voltage of about 0.5V. This phenomenon occurs because the threshold voltage of a device varies depending on the manufacturing process.
A transfer delay time is 260 ps/stage when VthP=xe2x88x920.10V and VthN=0.10V. When VthN =xe2x88x920.20V and VthP=xe2x88x920.10V, the transfer delay time becomes as fast as 200 ps. Conversely, when VthN=0.30V and VthP=xe2x88x920.10V, the transfer delay time significantly degrades to 947 ps. In this case, since the noise margin is 72 mV, it seems possible that the operation can be functionally performed. Nevertheless, since the gate speed decreases to ⅕, it is difficult to put a circuit of this type to practical use.
Since the logic circuit capable of being operated at 0.5V has little allowance for changes in its manufacturing process, but its low power consumption is advantageous during the stand-by time, it must be operated with a sufficient circuit margin during the operation time. To control the circuit margin and the transfer delay time within a preset range, a processing technique must be established. More specifically, the threshold voltage of the MOSFET must be controlled so that it does not vary by more than xc2x10.05V. However, this approach inevitably increases the cost of the semiconductor integrated circuit.
In a semiconductor integrated circuit for use in portable devices, low power consumption during operation time and stand-by time while satisfying the speed requirement during the operation is necessary. To attain low power consumption during the stand-by time, for example, the following two methods are known. Controlling a well potential by generating a voltage on a chip, having a magnitude of no less than the power supply voltage and no more than the ground potential of the logic circuit in the semiconductor integrated circuit is one method of attaining low power consumption during the stand-by time. Forming a power-supply switch using a FET having good off-characteristics is the second method. These methods are effective in attaining low power consumption during the stand-by time. However, if a power supply voltage of about 0.5V is used in order to attain the low power consumption during the operation time, the following problems exist:
1) A larger layout area is required due to the presence of the voltage generator;
2) The circuit stability decreases if the power supply voltage is dropped by a power switch FET; and
3) The circuit noise margin decreases if manufacturing process conditions for forming the 0.5V logic circuit vary.
Specifically, the circuit noise margin of the gate within the logic circuit operated at a power supply voltage of 0.5V is extremely low. Therefore, the functional operation margin is small when the device parameter is varied depending upon changes in manufacturing process conditions. As a result, a sufficient yield cannot be ensured as a semiconductor integrated circuit in a functional test.
When the yield is ensured to a certain level, if the device parameter varies, an operation speed will be changed. Even if the functional operation can be ensured, the yield of the chips satisfying the specification of speed decreases.
As described above, in the semiconductor integrated circuit for use in portable devices, since the allowance range of parameters for the device is narrow, element characteristics must be controlled strictly and a process step must be added. As a result, the cost inevitably increases. Furthermore, as compared to ordinary products, the yield of such a semiconductor integrated circuit is low. Therefore, the cost of the integrated circuit further increases.
Semiconductor integrated circuits consistent with the present invention substantially obviate one or more of the above described drawbacks of the related art.
In accordance with the present invention, there is provided a semiconductor integrated circuit comprising:
a semiconductor substrate having a first well of a first conductivity type, a second well of a first conductivity type, a first well of a second conductivity type, and a second well of a second conductivity type;
a complementary MIS logic circuit having first elements formed in the first well of the first conductivity type and second elements formed in the first well of the second conductivity type;
a logic-threshold-voltage generator for generating a voltage corresponding to a logic threshold voltage of the complementary MIS logic circuit, having a third element formed in the second well of the first conductivity type and a forth element formed in the second well of the second conductivity type;
a first voltage supply circuit for supplying a first voltage V having a magnitude between a first and a second power supply voltage to the complementary MIS logic circuit, wherein the second power supply voltage is a reference voltage and different from the first power supply voltage;
a differential amplification circuit wherein an output voltage of the logic-threshold-voltage generator is input to a positive terminal of the differential amplification circuit and wherein the first voltage V is input to a negative input terminal of the differential amplification circuit; and
a second voltage supply circuit for supplying a second voltage Vx, wherein
an output voltage of the differential amplification circuit is supplied to the first well of the first conductivity in which the first elements of the complementary MIS logic circuit is formed, and supplied to the second well of the first conductivity type, in which the third element of the logic-threshold-voltage generator is formed; and
the second voltage Vx is supplied to the first well of the second conductivity type in which the second elements of the complementary MIS logic circuit is formed and supplied to the second well of the second conductivity type, in which the forth element of the logic-threshold-voltage-generator is formed.
Also, in accordance with the present invention there is provided a semiconductor integrated circuit comprising:
a semiconductor substrate having a first well of a first conductivity type, a second well of a first conductivity type, a first well of a second conductivity type, and a second well of a second conductivity type;
a first, second, third and fourth power supply line to which a first, second, third, and fourth power supply outputting a voltage V1, V2, V3, and V4 is connected, respectively, wherein V1 greater than V2 greater than V3 greater than V4;
a complementary MIS logic circuit, wherein power supply terminals of the complementary MIS logic circuit are connected to the second power supply line and the third power supply line, the complementary MIS logic circuit including:
a second conductivity channel type MISFET formed in the first w ell of the first conductivity type; and
a first conductivity channel type MISFET formed in the first well of the second conductivity type;
a logic-threshold-voltage-generator for generating a voltage corresponding to a logic threshold voltage of the complementary MIS logic circuit, having a first circuit element formed in the second well of the first conductivity type and a second circuit element formed in the second well of the second conductivity type;
a first voltage supply circuit for supplying a first voltage V satisfying V2 greater than V greater than V3;
a first differential amplification circuit wherein an output voltage o f the logic-threshold-voltage-generator is input to a positive input terminal of the amplification circuit and wherein the first voltage V is input to a negative input terminal of the amplification circuit; and
a second voltage supply circuit for supplying a second voltage Vx,
wherein an output terminal of the differential amplification circuit is connected to the first and second well of the first conductivity; and
the second voltage vx is supplied to the first and second well of the second conductivity type.